期刊
JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS
卷 30, 期 17, 页码 16427-16438出版社
SPRINGER
DOI: 10.1007/s10854-019-02017-1
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资金
- Industrial Research and Consultancy Centre (IRCC), IIT Bombay [15IRCCSG002]
This paper reports the intermetallic growth and microvoid formation in the Cu-Sn layers, which were annealed at low temperatures (sub-200 degrees C) for durations varying from 120 to 1440 min. A 10 mu m thick tin was electrodeposited on copper samples. Both Cu6Sn5 and Cu3Sn IMCs were formed and had a non-uniform scalloped shaped profile but with different scallops sizes. Void growth was studied at three different locations, i.e., the Cu-Cu3Sn interface, within the Cu3Sn, and at the Cu3Sn-Cu6Sn5 interface. The void size in these locations increased with increasing annealing durations and temperatures due to the coalescence of nearby voids. The void fraction at the Cu-Cu3Sn and Cu3Sn-Cu6Sn5 interfaces was observed to decrease, whereas the void fraction within the Cu3Sn IMC increased with increasing annealing durations. The largest voids were seen at the Cu-Cu3Sn interface, while the highest void fraction was found within the Cu3Sn IMC. The overall void size and void fractions for all experimental conditions were always smaller than 3 mu m(2) and 1.44 mu m(-1), respectively. The obtained results can be used in the hermetic packaging of MEMS devices performed at sub-200 degrees C. Processing at these low temperatures result in reduced thermo-mechanical stress and also eliminate the molten tin squeezing-out from the bonding zone, which is a known issue in Cu-Sn solid-liquid inter-diffusion bonding performed at temperature > 232 degrees C.
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