Approach for fabricating JLT using chemically deposited cadmium sulphide and titanium dioxide

Cadmium sulphide and titanium dioxide-based junctionless transistor (JLT) has been demonstrated by using simple and low-cost chemical bath deposition method. The morphological and structural study has been performed to speculate the crystallinity and the topography of individual layers of the proposed device. The optimised sputtering conditions lead to the formation of source and drain electrical contacts of the device. The fabricated device successfully functionalised as a p-channel JLT. At the source-to-drain voltage of -50 V, the ON-state drive current and OFF-state leakage current of the fabricated JLT are found to be -6 mu A and 1.3 nA, respectively.