期刊
IEEE TRANSACTIONS ON COMPUTERS
卷 68, 期 5, 页码 729-739出版社
IEEE COMPUTER SOC
DOI: 10.1109/TC.2018.2882774
关键词
Quantum computing; quantum arithmetic; integer multiplication; conditional adder; clifford plus T gates; quantum circuits
Quantum circuits of many qubits are extremely difficult to realize; thus, the number of qubits is an important metric in a quantum circuit design. Further, scalable and reliable quantum circuits are based on fault tolerant implementations of quantum gates such as Clifford+T gates. An efficient quantum circuit saves quantum hardware resources by reducing the number of T gates without substantially increasing the number of qubits. This work presents a T-count optimized quantum circuit for integer multiplication with only 4 . n + 1 qubits and no garbage outputs. The proposed quantum multiplier design reduces the T-count by using a novel quantum conditional adder circuit. Also, where one operand to the conditional adder is zero, the conditional adder is replaced with a Toffoli gate array to further save T gates. Average T-count savings of 46: 12, 47: 55, 62: 71 and 26.30 percent are achieved compared to the recent works by Kotiyal et al., Babu, Lin et al., and Jayashree et al., respectively.
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