4.6 Article

A Nonuniform Sparse 2-D Large-FOV Optical Phased Array With a Low-Power PWM Drive

期刊

IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 54, 期 5, 页码 1200-1215

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2019.2896767

关键词

Free-space optical communication; integrated optics; light detection and ranging (LiDAR); nonuniform sparse aperture; optical phased array (OPA); optical switching devices; optoelectronics; phased array imaging systems; silicon photonics

资金

  1. Caltech Innovation Initiative

向作者/读者索取更多资源

Integrated optical phased arrays (OPAs) capable of adaptive beamforming and beam steering enable a wide range of applications. For many of these applications, a large scale 2-D OPA with full phase control for each radiating element is essential to achieve a functional low-cost solution. However, the scalability of such OPAs has been hampered by the optical feed distribution difficulties in a planar photonics process, as well as the high power consumption associated with having a large number of phase control units. In this paper, we present a two-chip solution low-power scalable OPA with a nonuniform sparse aperture, providing radiation pattern adjustment and feed distribution feasibility in a CMOS compatible silicon photonics process. The demonstrated OPA with a 128-element aperture achieves the highest reported grating-lobe-free field-of-view (FOV)-to-beamwidth ratio of 16 degrees/0.8 degrees, which is equivalent to a 484-element uniform array. This translates to at least 400 resolvable spots, 30 times more than the state-of-the-art 2-D OPAs. Moreover, by utilizing compact phase shifters in a row-column power delivery grid, we reduce the number of required drivers from 144 to 37. A high-swing pulsewidth modulation (PWM) driving circuit featuring breakdown voltage multipliers and soft turnon activation significantly reduces the power consumption of the system. The electronic driver chip and the integrated photonic chip are fabricated on a 65-nm CMOS process and a thick silicon-on-insulator (SOI) silicon photonics process, occupying 1.7 mm(2) and 2.08 mm(2) of active area, respectively.

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