All inorganic solution processed three terminal charge trapping memory device

We demonstrate charge trapping memory devices comprising aluminum oxide phosphate (ALPO) blocking/indium gallium zinc oxide charge-trapping/ALPO tunneling layers with a bottom-gated architecture fabricated by sol-gel process technique at temperatures as low as 300 degrees C. The memory device offers a large memory hysteresis of 13.5 V in the I-d-V-g curve when the gate voltage is swept from -20 to +30 V and back. The true program-erase (P/E) window of 7 V is established for the P/E square pulse of +/- 20 V s(-1). Good retention characteristic is confirmed within the experimental limit of 10(4) s. The P/E mechanism is illustrated by the complete band structure of the memory devices. We also demonstrate a control device without a charge trapping layer, which shows excellent thin film transistor characteristics. Published under license by AIP Publishing.