4.7 Article

Compact Real-Time Inter-Frame Histogram Builder for 15-Bits High-Speed ToF-Imagers Based on Single-Photon Detection

期刊

IEEE SENSORS JOURNAL
卷 19, 期 6, 页码 2181-2190

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSEN.2018.2885960

关键词

Shifted inter-frame histogram (SifH); real-time time-of-flight (ToF) estimation; ToF image sensor; single-photon avalanche-diode (SPAD)

资金

  1. Office of Naval Research (ONR), USA [N000141410355]
  2. Spanish MINECO
  3. European Region Development Fund (ERDF/FEDER) [TEC2015-66878-C3-1-R]
  4. Junta de Andalucia through the SmartCIS3D Project [TIC 2338-2013]
  5. EU-REA through the Achieve Project (EU H2020 MSCA-ITN) [765866]

向作者/读者索取更多资源

Time-of-flight (ToF) image sensors based on single-photon detection, i.e., SPADs, require some filtering of pixel readings. Accurate depth measurements are only possible if the jitter of the detector is mitigated. Moreover, the time stamp needs to be effectively separated from uncorrelated noise, such as dark counts and background illumination. A powerful tool for this is building a histogram of a number of pixel readings. Future generation of ToF imagers are seeking to increase spatial and temporal resolution along with the dynamic range and frame rate. Under these circumstances, storing the complete histogram for every pixel becomes practically impossible. Considering that most of the information contained by the histogram represents noise, we propose a highly efficient method to store just the relevant data required for the ToF computation. This method makes use of the shifted inter-frame histogram. It requires a memory as low as 128 times smaller than storing the complete histogram if the pixel values are coded on up to 15 bits. Moreover, a fixed 2(8) words memory is enough to process histograms containing up to 2(15) bins. In exchange, the overall frame rate only decreases to one half. The hardware implementation of this algorithm is presented. Its remarkable robustness for a low SNR of the ToF estimation is demonstrated by Matlab simulations and FPGA implementation using input data from a SPAD camera prototype.

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