期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 54, 期 1, 页码 65-74出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2018.2872539
关键词
Crystal oscillator (XO); digitally controlled oscillator (DCO); duty-cycle correction; frequency quadrupler; injection-locked clock multiplier (ILCM); jitter; least mean square (LMS); ring oscillator (RO)
资金
- Analog Devices
Implementation of low-noise power-efficient clock multipliers requires low-noise high-frequency reference clocks. This paper presents ways to generate such reference clocks at four times the frequency of a standard crystal oscillator (XO) output frequency. Using extensive digital correction techniques, a 216-MHz reference clock with an integrated jitter of 77fs(rms) is generated from a 54-MHz Pierce XO. A ring oscillator-based injection locking clock multiplier driven by the proposed quadrupler is used to demonstrate the efficacy of the quadrupler. Fabricated in a 65-nm CMOS process, the proposed clock multiplier occupies an active area of 0.16 mm(2) and achieves 366fs(rms) integrated jitter at 4.752-GHz output frequency while consuming 6.5-mW power from a 1.0-V supply of which 1.5 mW is consumed in the quadrupler.
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