期刊
APPLIED SCIENCES-BASEL
卷 9, 期 1, 页码 -出版社
MDPI
DOI: 10.3390/app9010020
关键词
field-programmable gate array (FPGA); time-to-digital converter (TDC); tapped-delay line (TDL); dual delay lines (DDL); run-time calibration; differential non-linearity (DNL)
类别
资金
- Ministry of Science and Technology of Taiwan [107-2221-E-182-066]
- Chang Gung Memorial Hospital-Linkou [CMRPD2H0051, CIRPD2F0013, CMRPD2G0312]
This paper presents a time-to-digital converter (TDC) based on a field programmable gate array (FPGA) with a tapped delay line (TDL) architecture. This converter employs dual delay lines (DDLs) to enable real-time calibrations, and the proposed DDL-TDC measures the statistical distribution of delays to permit the calibration of nonuniform delay cells in FPGA-based TDC designs. DDLs are also used to set up alternate calibrations, thus enabling environmental effects to be immediately accounted for. Experimental results revealed that relative to a conventional TDL-TDC, the proposed DDL-TDC reduced the maximum differential nonlinearity by 26% and the integral nonlinearity by 30%. A root-mean-squared value of 32 ps was measured by inputting the constant delay source into the proposed DDL-TDC. The proposed scheme also maintained excellent linearity across a range of temperatures.
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