4.6 Article

On Practical Issues for Stochastic STDP Hardware With 1-bit Synaptic Weights

期刊

FRONTIERS IN NEUROSCIENCE
卷 12, 期 -, 页码 -

出版社

FRONTIERS MEDIA SA
DOI: 10.3389/fnins.2018.00665

关键词

spiking neural networks; spike timing dependent plasticity; stochastic learning; feature extraction; neuromorphic systems

资金

  1. EU H2020 [644096 ECOMODE, 687299 NEURAM3]
  2. Samsung Advanced Institute of Technology grant NPP
  3. Spanish grant from the Ministry of Economy and Competitivity [TEC2015-63884-C2-1-P]
  4. Spanish grant from the Ministry of Economy and Competitivity (European Regional Development Fund)
  5. FPI scholarship from the Spanish Ministry of Economy and Competitivity

向作者/读者索取更多资源

In computational neuroscience, synaptic plasticity learning rules are typically studied using the full 64-bit floating point precision computers provide. However, for dedicated hardware implementations, the precision used not only penalizes directly the required memory resources, but also the computing, communication, and energy resources. When it comes to hardware engineering, a key question is always to find the minimum number of necessary bits to keep the neurocomputational system working satisfactorily. Here we present some techniques and results obtained when limiting synaptic weights to 1-bit precision, applied to a Spike-Timing-Dependent-Plasticity (STDP) learning rule in Spiking Neural Networks (SNN). We first illustrate the 1 -bit synapses STDP operation by replicating a classical biological experiment on visual orientation tuning, using a simple four neuron setup. After this, we apply 1-bit STDP learning to the hidden feature extraction layer of a 2-layer system, where for the second (and output) layer we use already reported SNN classifiers. The systems are tested on two spiking datasets: a Dynamic Vision Sensor (DVS) recorded poker card symbols dataset and a Poisson-distributed spike representation MNIST dataset version. Tests are performed using the in-house MegaSim event-driven behavioral simulator and by implementing the systems on FPGA (Field Programmable Gate Array) hardware.

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