Border trap evaluation for SiO2/GeO2/Ge gate stacks using deep-level transient spectroscopy

A border trap (BT) evaluation method was established for SiO2/GeO2/Ge gate stacks by using deep-level transient spectroscopy with a lock-in integrator. Ge metal-oxide-semiconductor capacitors (MOSCAPs) with SiO2/GeO2/Ge gate stacks were fabricated by using different methods. The interface trap (IT) and BT signals were successfully separated based on their different dependences on the intensity of injection pulses. By using p-type MOSCAPs, BTs at the position of 0.4 nm from the GeO2/Ge interface were measured. The energy of these BTs was centralized at the position near to the valence band edge of Ge, and their density (N-bt) was in the range of 10(17)-10(18) cm(-3). By using n-type MOSCAPs, BTs at the position range of 2.8-3.4 nm from the GeO2/Ge interface were measured, of which N-bt varied little in the depth direction. The energy of these BTs was distributed in a relatively wide range near to the conduction band edge of Ge, and their N-bt was approximately one order of magnitude higher than those measured by p-MOSCAPs. This high N-bt value might originate from the states of the valence alternation pair with energy close to 1 eV above the conduction band edge of Ge. We also found that Al post metallization annealing can passivate both ITs and BTs near to the valence band edge of Ge but not those near to the conduction band edge. Published by AIP Publishing.