期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 53, 期 12, 页码 3517-3527出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2018.2871143
关键词
5G communications; bandpass delta-sigma modulator (DSM); digital-to-analog converter; digital pre-distortion (DPD); high resolution; high speed; hybrid; RF; time interleaving; timing errors; tunable passbands
This paper presents a hybrid digital-to-analog converter (DAC) architecture with a tunable bandpass delta-sigma modulator (DSM) to synthesize channelized signals over a wide frequency range with high linearity and a low in-band noise floor. Due to the mostly digital architecture, this DAC topology favors technology scaling. The DSM uses a successive pipeline structure with time-interleaving techniques to achieve a 12-GS/s data rate and overall 16-bit DAC resolution. To improve the linearity at high frequencies, an inverse-sinc-shaped digital pre-distortion (DPD) scheme is used to better approximate and compensate the timing errors. The DAC can be configured for single- or dual-rate operation modes to tradeoff different input data rates with DAC linearity and spectral images. The prototype was fabricated in 65-nm CMOS technology with an analog area of 0.1 mm(2) and <250-mW analog power consumption. It achieved IM3 of -85 to -67 dBc over the Nyquist band, and the spurious-free dynamic range remains >60 dBc up to a 4.2-GHz signal frequency at 12 GS/s in the single-rate mode thanks to the hybrid structure and proposed DPD techniques.
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