Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging?

Current status and challenges of aggressive equivalent-oxide-thickness (EOT) scaling of high-kappa gate dielectrics via higher-kappa (>20) materials and interfacial layer (IL) scavenging techniques are reviewed. La-based higher-kappa materials show aggressive EOT scaling (0.5-0.8 nm), but with effective workfunction (EWF) values suitable only for n-type field-effect-transistor (FET). Further exploration for p-type FET-compatible higher-kappa materials is needed. Meanwhile, IL scavenging is a promising approach to extend Hf-based high-kappa dielectrics to future nodes. Remote IL scavenging techniques enable EOT scaling below 0.5 nm. Mobility-EOT trends in the literature suggest that short-channel performance improvement is attainable with aggressive EOT scaling via IL scavenging or La-silicate formation. However, extreme IL scaling (e.g., zero-IL) is accompanied by loss of EWF control and with severe penalty in reliability. Therefore, highly precise IL thickness control in an ultra-thin IL regime (<0.5 nm) will be the key technology to satisfy both performance and reliability requirements for future CMOS devices.