期刊
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY
卷 4, 期 4, 页码 581-587出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCPMT.2014.2298031
关键词
Cu electroplating; Cu filling defects; Cu seed layer; failure modes; Si etch; through-silicon via ( TSV).
In this paper, we report through-silicon via (TSV) Cu filling failure modes and categorize them into three major regions based on their causes. First, Si etch-related region for the TSV defining. Si etch defects, such as bottom corner notch, Si grass at the bottom, surface roughness, and sponge-like defect, cause Cu seed layer loss at the defect areas. It causes electrical disconnection resulting in the TSV Cu filling failure. Second, Cu seed layer-related region. Defects include poor Cu seed layer step coverage and oxidation of the Cu seed layer from the Cu seed layer deposition until the TSV Cu electroplating from the Cu seed layer deposition. They result in aggrandizing terminal effect, which makes Cu ion reduction at the TSV bottom difficult. Third, Cu electroplating-related region. The most important factor in this region is chemical concentration control because the TSV Cu filling by bottom up filling mainly depends on the cooperation of three additives of suppressor, accelerator, and leveler. Another important factor in the region is current density ramp up rate. It is critical to ramp up the current density with an appropriate rate to prevent pinchoff plating causing voids inside the TSVs. These regions are closely connected with each other and the relationship needs to be understood to overcome the TSV Cu filling failure.
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