期刊
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY
卷 2, 期 6, 页码 956-963出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCPMT.2011.2177663
关键词
Chemical-mechanical polishing; Cu slurry; polishing; through silicon via
类别
资金
- Electronics & Optoelectronics Research Laboratory, Industrial Technology Research Institute
In this paper, the optimization of Cu chemical-mechanical polishing (CMP) performance (dishing) for the removal of thick Cu-plating overburden due to Cu plating for deep through silicon via (TSV) in a 300-mm wafer is investigated. Moreover, backside isolation oxide CMP for TSV Cu exposure is examined. To obtain a minimum Cu dishing on the TSV region, a proper selection of Cu slurries is proposed for the current two-step Cu-polishing process. First, a bulk of Cu is removed with the slurry of high Cu removal rate and second, the Cu surface is planarized with the slurry of high Cu passivation capability. The Cu dishing can be improved up to 97% for the 10-mu m-diameter TSVs on a 300-mm wafer. The dishing/erosion of the metal/oxide can be reduced with respect to a correspondingly optimized Cu-plating overburden for TSVs and redistribution layers. Cu metal dishing can be drastically reduced once the Cu overburdens are increased to a critical thickness. For backside isolation oxide CMP for TSV Cu exposure, the results show that the Cu studs of TSVs with a larger TSV diameter still keep in a plateau-like shape after CMP.
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