Analysis of temperature dependent hysteresis in MoS2 field effect transistors for high frequency applications

Thermal and hysteresis effects are studied for the first time in Al2O3 top-gated, CVD grown monolayer MoS2 field effect transistors (FETs). Stressing with an applied bias reversed the hysteresis rotation in the high temperature I-ds-V-gs transfer characteristics and this behavior, indicative of a multilevel trap model, was explained by charge carriers interacting with traps possibly at the MoS2/dielectric interface and within the CVD grown MoS2. High temperature FET characteristics measured up to 125 degrees C demonstrated pinch-off degradation and the influence of trapping/detrapping rates in both the top and bottom gate dielectric. This indicates the importance of maintaining oxide and interface quality for good FET performance. Published by Elsevier Ltd.