期刊
SOLID-STATE ELECTRONICS
卷 90, 期 -, 页码 86-93出版社
PERGAMON-ELSEVIER SCIENCE LTD
DOI: 10.1016/j.sse.2013.02.047
关键词
Junctionless transistors (JLTs); Threshold voltage (V-th); Flat-band voltage (V-fb); Drain induced barrier lowering (DIBL); Low field mobility (mu(0)); Channel doping level
资金
- National Research Foundation of Korea [2010-50174, 2011-0031638] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
Several electrical parameters characterize device performance, electron transport and doping level in MOS transistors. In this paper, Junctionless Transistors (JLTs) fabricated on (100) silicon on insulator (SOI) wafer with 145 nm thick BOX and 9 nm silicon thickness were considered. Parameter extraction methodologies were revisited in order to account for the unique electrical properties of JLT devices. The deduced parameters, such as threshold voltage, flat-band voltage, drain induced barrier lowering (DIBL), low field mobility and channel doping level, are shown to reveal the specific features of JLT compared to conventional inversion-mode transistors. (C) 2013 Elsevier Ltd. All rights reserved.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据