期刊
SOLID-STATE ELECTRONICS
卷 53, 期 10, 页码 1112-1115出版社
PERGAMON-ELSEVIER SCIENCE LTD
DOI: 10.1016/j.sse.2009.06.004
关键词
CMOS; Series resistance; Ultra-thin body (UTB); Silicon-on-insulator (SOI); Elevated source/drain; Transmission line model; Specific contact resistivity
Optimization of the series resistance of silicide contact structure in ultra-thin body (UTB) silicon-on-insulator (SOI) MOSFET with elevated source/drain (S/D) is examined through theoretical analysis and 2-dimensional simulation. It is found that the optimum silicide/Si interface position, which exhibits lowest parasitic series resistance, can be located at inside of 501 layer under the surface as the effective contact length is scaled down further below 100 nm regime. The closed-form analytical expressions derived from modified transmission line model principle provide a guideline for optimum design of silicide thickness and contact parameters in self-aligned silicide technology. (C) 2009 Elsevier Ltd. All rights reserved.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据