Graphene-Graphene Oxide Floating Gate Transistor Memory

A novel transparent, flexible, graphene channel floating-gate transistor memory (FGTM) device is fabricated using a graphene oxide (GO) charge trapping layer on a plastic substrate. The GO layer, which bears ammonium groups (NH3+), is prepared at the interface between the crosslinked PVP (cPVP) tunneling dielectric and the Al2O3 blocking dielectric layers. Important design rules are proposed for a high-performance graphene memory device: i) precise doping of the graphene channel, and ii) chemical functionalization of the GO charge trapping layer. How to control memory characteristics by graphene doping is systematically explained, and the optimal conditions for the best performance of the memory devices are found. Note that precise control over the doping of the graphene channel maximizes the conductance difference at a zero gate voltage, which reduces the device power consumption. The proposed optimization via graphene doping can be applied to any graph ene channel transistor-type memory device. Additionally, the positively charged GO (GO NH3+) interacts electrostatically with hydroxyl groups of both UV-treated Al2O3 and PVP layers, which enhances the interfacial adhesion, and thus the mechanical stability of the device during bending. The resulting graphene graphene oxide FGTMs exhibit excellent memory characteristics, including a large memory window (11.7 V), fast switching speed (1 mu s), cyclic endurance (200 cycles), stable retention (1W s), and good mechanical stability (1000 cycles).