Design and verification of a thermoelectric energy harvester with stacked polysilicon thermocouples by CMOS process

State-of-the-art CMOS semiconductor has been pushing below 32 nm process, and stacked system (also called chip stacking) will be the mainstream in IC foundry. Recent design of micro-thermoelectric generator (mu TEG) is by using co-planar thermocouples to harvest ambient heat. A mu TEG design based on stacked polysilicon thermocouples is developed in this work, in which the p- and n-thermolegs of a thermocouple are stacked and insulated. A thermal model is applied to analyze the optimal thermocouple size by matching their thermal resistance and electrical resistance. Analysis shows that the maximum power factor and voltage factor of an optimal thermocouple 100 mu m x 4 mu m x 0.275/0.18 mu m (length x width x thickness for p-/n-thermolegs) is 0.0473 mu W/cm(2) K(2) and 3.952 V/cm(2) K, respectively. The voltage factor is about 142% of that in co-planar design. Multiple thermocouples can thus be stacked for higher performance. Design verification by TSMC 0.35 mu m 2P4M (2-poly and 4-metal layers) standard CMOS process shows that the stacked design with 120 mu m x 4 mu m x 0.275/0.18 mu m thermocouples can achieve the power factor 0.0427 mu W/cm(2) K(2) and voltage factor 3.417 V/cm(2) K. (C) 2009 Elsevier B.V. All rights reserved.