Epitaxial growth of Ge thick layers on nominal and 6° off Si(001); Ge surface passivation by Si

We have grown various thickness Ge layers on nominal and 6 degrees off Si(0 0 1) substrates using a low-temperature/high-temperature strategy followed by thermal cycling. A combination of 'mounds' and a perpendicular cross-hatch were obtained on nominal surfaces. On 6 degrees off surfaces, three sets of lines were obtained on top of the 'mounds': one along the < 1 1 0 > direction perpendicular to the misorientation direction and the other two at similar to 4.5 degrees on each side of the < 1 1 0 > direction parallel to the misorientation direction. The surface root mean square roughness was less than 1 nm for 2.5 mu m thick nominal and 6 degrees off Ge layers. Those slightly tensily strained Ge layers (R similar to 104%) were characterized by 5 x 10(7) cm(-2) (as-grown layers) -10(7) cm(-2) (annealed layers) threading dislocation densities, independently of the substrate orientation. We have then described the 550 degrees C/650 degrees C process used to passivate nominal Ge(0 0 1) surfaces with Si prior to gate stack deposition. An similar to 5 angstrom thick SiGe interfacial layer is self-limitedly grown at 550 degrees C and then thickened at 650 degrees C (5 angstrom min(-1)) thanks to SiH2Cl2 at 20 Torr. Such a Ge surface passivation yields state-of-the-art p-type metal oxide semiconductor field effect transistors provided that 15 angstrom Si layer thickness is not exceeded. For higher thickness, elastic strain relaxation (through the formation of numerous 2D islands) occurs, followed by plastic relaxation (for a 35 angstrom thick Si layer).