相关参考文献
注意：仅列出部分参考文献，下载原文获取全部文献信息。Stress Liner Effects for 32-nm SOI MOSFETs With HKMG
Ming Cai et al.
IEEE TRANSACTIONS ON ELECTRON DEVICES (2010)
Stress Memorization Technique-Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process
Claude Ortolland et al.
IEEE TRANSACTIONS ON ELECTRON DEVICES (2009)
Manufacturable processes for ≤ 32-nm-node CMOS enhancement by synchronous optimization. of strain-engineered channel and external parasitic resistances
Atif M. Noori et al.
IEEE TRANSACTIONS ON ELECTRON DEVICES (2008)
Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors
ML Lee et al.
JOURNAL OF APPLIED PHYSICS (2005)
A 90-nm logic technology featuring strained-silicon
SE Thompson et al.
IEEE TRANSACTIONS ON ELECTRON DEVICES (2004)
Six-band k•p calculation of the hole mobility in silicon inversion layers:: Dependence on surface orientation, strain, and silicon thickness
MV Fischetti et al.
JOURNAL OF APPLIED PHYSICS (2003)
分享论文
