期刊
SCIENCE CHINA-INFORMATION SCIENCES
卷 54, 期 5, 页码 990-1003出版社
SCIENCE PRESS
DOI: 10.1007/s11432-011-4231-x
关键词
CMOSFETs; silicon; strain; carbon; germanium; silicon on insulator technology; FDSOI; FinFET; multigates; nanowires; wafer bonding; 3D sequential integration
资金
- Crolles 2 Alliance
- LETI-ST Microelectronics-IBM Alliance
- Convention with French Ministry of Industry and Finance [NANO2012]
- INALOGIC Competitively Pole
- French National Research Agency Carnot Institute
The nanoelectronics industry is facing historical challenges to scale down CMOS devices to meet demands for low voltage, low power, high performance and increased functionality. Using new materials and devices architectures is necessary. HiK gate dielectrics and metal gates have been introduced and have shown their ability to reduce power consumption. Fully depleted ultra-thin SOI devices are a good alternative to bulk for low power applications. Multigate devices are the current goal in device architecture to increase MOSFET drivability, reduce power, and allow new opportunities for future applications. Thin film based solutions will be necessary in the future because of fundamental limitations on gate capacitance scaling and system integration requirements. Exploiting 3D device stacking via wafer bonding could be a good way to introduce new materials (HiK, strained Si, hybrid orientations, Ge, III-Vs, Carbon-based materials, graphene and CNTs, and functional molecules) and continue increasing integration density. Si based CMOS will be scaled beyond the ITRS as the System-on-Chip/Wafer Platform.
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