Si nanowire FET and its modeling

Because of its ability to effectively suppress off-leakage current with its gate-around configuration, the Si nanowire FET is considered to be the ultimate structure for ultra-small CMOS devices to the extent that the devices would be approaching their downsized limits. Recently, several experimental studies of Si nanowire FETs with on-currents much larger than those of planar MOSFETs have been published. Consequently, Si nanowire FETs are now gaining significant attention as the most promising candidate for mainstream CMOS devices in the 2020s. To enable the introduction of the Si nanowire FETs into integrated circuits, good compact models, which circuit designers can easily handle, are essential. However, it is a very challenging task to establish such a compact model, because the I (D)-V (D) characteristics of Si nanowire FETs are affected by the band structure of the nanowire, which is very sensitive to the nanowire diameter, cross-sectional shape, crystal orientation, mechanical stress and interface states. In this paper, the recent status of research on Si nanowire FETs in experimental and theoretical studies is described.