期刊
NANO LETTERS
卷 13, 期 12, 页码 5967-5971出版社
AMER CHEMICAL SOC
DOI: 10.1021/nl403142v
关键词
Graphene; thin-film semiconductor; heterojunction transistor; wafer-scale integration; low-power electronics
Graphene heterostructures in which graphene is combined with semiconductors or other layered 2D materials are of considerable interest, as a new class of electronic devices has been realized. Here we propose a technology platform based on graphene thin-film-semiconductor metal (GSM) junctions, which can be applied to large-scale and power-efficient electronics compatible with a variety of substrates. We demonstrate wafer-scale integration of vertical field-effect transistors (VFETs) based on graphene In-Ga-Zn-O (IGZO)-metal asymmetric junctions on a transparent 150 x 150 mm(2) glass. In this system, a triangular energy barrier between the graphene and metal is designed by selecting a metal with a proper work function. We obtain a maximum current on/off ratio (I-on/I-off) up to 106 with an average of 3010 over 2000 devices under ambient conditions. For low-power logic applications, an inverter that combines complementary n-type (IGZO) and p-type (Ge) devices is demonstrated to operate at a bias of only 0.5 V.
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