Rational Defect Introduction in Silicon Nanowires

The controlled introduction of planar defects, particularly twin boundaries and stacking faults, in group IV nanowires remains challenging despite the prevalence of these structural features in other nanowire systems (e.g., II-VI and III-V). Here we demonstrate how user-programmable changes to precursor pressure and growth temperature can rationally generate both transverse twin boundaries and angled stacking faults during the growth of < 111 > oriented Si nanowires. We leverage this new capability to demonstrate prototype defect superstructures. These findings yield important insight into the mechanism of defect generation in semiconductor nanowires and suggest new routes to engineer the properties of this ubiquitous semiconductor.