An accurate MOSFET aging model for 28 nm integrated circuit simulation

MOSFET device aging represents a significant challenge for the IC industry, being increasingly more responsible for reliability failure in advanced process technology nodes. As the device electrical characteristics, such as threshold voltage and drain current, degrade with time, circuit performance also deteriorates, resulting in shorter lifetime and narrower safety margins between requirements and actual product reliability. Major device aging mechanisms include the hot-carrier injection (HCI), the negative bias-temperature instability (NBTI) for p-channel MOSFETs, and the positive bias-temperature instability (PBTI) for n-channel devices. HCI in NMOS and PMOS has been known for many years. In the presence of high electric fields, carriers are injected from the drain end of the channel into the gate dielectric, changing its electrical properties over time. PMOS NBTI has been studied in the past, and it continues to present a challenge for today's technologies. NMOS PBTI is a phenomenon notably present in high-k metal-gate stacks. The partial recovery of degradation, an effect important for both phenomena, has been particularly challenging to model for circuit simulation, and not addressing it may result in overly pessimistic circuit lifetime predictions. In this paper we present an accurate, physics-based MOSFET aging model that encompasses degradation due to HCI, NBTI and PBTI. The model formulation on bias, geometry and temperature, and a unique methodology for modeling the AC partial-recovery effect of BTI are detailed and analyzed. The extraction methodology of the aging model parameters is further described. The model is implemented in an efficient MOSRA flow for SPICE and Fast SPICE circuit simulation, which has been successfully used to improve IC reliability-related yield in numerous 28 nm tapeouts. (C) 2011 Elsevier Ltd. All rights reserved.