期刊
MICROELECTRONICS JOURNAL
卷 44, 期 10, 页码 930-940出版社
ELSEVIER SCI LTD
DOI: 10.1016/j.mejo.2013.03.002
关键词
Analog CMOS; Flipped voltage followers; Current comparators; Winner-Takes-All circuits; Current conveyors
资金
- National Council of Science and Technology (CONACyT) of Mexico [181201-Y]
- Program for Faculty Improvement (PROMEP) of Mexico [F-PROMEP-39/Rev-03]
A compact differential flipped voltage follower (DFVF) with low power consumption, capable to deliver currents several orders of magnitude larger than its quiescent current and with large capacitive loads is presented. In the proposed circuit, a current comparator activates an auxiliary transistor whenever is required to hand over additional current and reach class-AB operation. Furthermore, Miller compensation is performed, by taking advantage of the large impedance node of the comparator it is possible to reduce forty times the compensation capacitor compared to other topologies under the same conditions. The proposed architecture is validated by post-layout simulations using the parameters of an ON SEMI, double-poly, three metal layers, 0.5 mu m CMOS technology and the Pelgrom's mismatch model. A Winner-Takes-All circuit, a median filter and a current conveyor are presented as examples of application of the proposed topology. (C) 2013 Elsevier Ltd. All rights reserved.
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