期刊
MICROELECTRONIC ENGINEERING
卷 87, 期 3, 页码 496-500出版社
ELSEVIER
DOI: 10.1016/j.mee.2009.07.003
关键词
Cu/low-k stacking structure; Flip chip package; Finite element analysis; Global-local technique
As the electronics industry continues its efforts in miniaturizing the integrated circuit (IC), an IC chip with copper/low-k stacked Back End of Line (BEoL) structures has been developed for reducing R-C delay in order to obtain high-speed signal communication. However, its reliability might become a concern owing to the considerably lower adhesive strength, as well as the greater coefficient of thermal expansion (CTE) of the low-k materials. In this paper. the global-local finite element method, specified boundary condition (SBC) method, is employed as a bridge to estimate the impact from package level to the deep sub-micron BEoL structure of the flip chip package. The results show that the defect in the stacking structure at the center of the silicon has a lower tendency to crack than that at the corner region. In addition, the higher underfill CTE shows the disadvantage of the defect. (C) 2009 Elsevier B.V. All rights reserved.
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