4.4 Article Proceedings Paper

Carbon nanotubes for nanoscale low temperature flip chip connections

期刊

MICROELECTRONIC ENGINEERING
卷 87, 期 3, 页码 438-442

出版社

ELSEVIER SCIENCE BV
DOI: 10.1016/j.mee.2009.05.027

关键词

CNT bumps; Selective growth; Flip chip bonding; ALD

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In this work we demonstrate a new approach for ultra fine flip chip interconnections based on carbon nanotubes as a wiring material. In contrast to other works we show patterned growth of multi walled CNTs on substrates with pre-structured bond pads including a complete metallization system for electrical characterization. Furthermore, we succeeded achieving a reliable flip chip connection between CNT-covered contact pads and metal pads at temperatures lower than 200 degrees C. Our goal is a reversible electrical and mechanical chip assembly with CNT bumps. For bonding experiments and electrical characterization a test structure with a damascene metallization including a layer stack of TiN/Cu/TiN was prepared. For CNT growth a thin nickel catalyst layer was selectively deposited with sputtering and a lift-off technique on the contact pads. The CNTs were grown by thermal CVD with ethylene as carbon source. CNT growth parameters like catalyst thickness, gas composition, growth time and temperature were optimized to get dense CNT growth. The metal bumps of the counter chip consist of electroless deposited Ni. With the selected layout we can obtain daisy chain and four-point measurements for lossless determination of single contact resistance. We have obtained reliable electrical contacts with relatively small resistance reaching values as low as 2.2 Omega. As CNT-quality is strongly dependent on the growth temperature we observed a strong change in resistivity of the flip chip connection as the growth temperature was varied. Reliability tests showed long time stability under thermal stress proving a reliable electrical contact between the contact pads. There is an appropriate Potential for further optimization of the CNT bump resistance and applying this technology for IC-devices. (C) 2009 Elsevier B.V. All rights reserved.

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