期刊
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B
卷 27, 期 6, 页码 2790-2794出版社
A V S AMER INST PHYSICS
DOI: 10.1116/1.3237138
关键词
elemental semiconductors; Ge-Si alloys; high electron mobility transistors; nanolithography; semiconductor heterojunctions; silicon; soft lithography; sputter etching; tunnel transistors
资金
- U. S. Defense Advanced Research Program Agency (DARPA) [FA8650-08-C-7806]
Fabrication of an asymmetric source/drain structure is important to heterojunction tunneling transistors but is extremely difficult to achieve reliably due to the stringent requirement of nanometer overlay alignment. Here the authors propose and demonstrate a simple self-aligned asymmetric nanotrench fabrication method, which has achieved a 10 nm wide (35 nm deep) trench in source region with an alignment accuracy better than 3 nm. The method is based on asymmetric shadow evaporation of the metal with the gate as a mask, creating an area uncovered by the metal only in the source but not in the drain, and a subsequent reactive ion etching with the evaporated metal as the etching mask. The accuracy of this method was found experimentally and theoretically to be within 5 nm.
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