Spectral reflectometry for metrology of three-dimensional through-silicon vias

The technology for semiconductor device packaging is rapidly advancing in response to increasing demand for smaller and thinner electronic devices. Three-dimensional chip stacking that uses through-silicon vias (TSVs) is a key area of technical focus, and the high-density TSV (HDTSV) is a major enabler of three-dimensional (3-D) integrated circuit technology. The ongoing development of this novel technology has created a need for noncontact characterization. One of the main challenges for 3-D TSV metrology is measuring high aspect ratio features that limit conventional optical microscopy techniques. We demonstrate the use and enhancement of an existing wafer metrology tool, a spectral reflectometer, by developing and implementing theoretical models and measurement algorithms for inspection of HDTSVs. It is capable of measuring the depth of vias, and can also be used for the estimation of bottom roughness and bottom shapes of vias through the model fitting. Our nondestructive solution has measured TSV diameters as small as 3 mu m and aspect ratios > 16.5: 1. Submicron depth measurement accuracy has been verified in the range of 30 to 60 mu m on via depth. Metrology results from actual wafers formed from 3-D interconnect processing are presented. (C) The Authors. Published by SPIE under a Creative Commons Attribution 3.0 Unported License. Distribution or reproduction of this work in whole or in part requires full attribution of the original publication, including its DOI.