期刊
JOURNAL OF LIGHTWAVE TECHNOLOGY
卷 32, 期 18, 页码 3161-3174出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JLT.2014.2336234
关键词
Insertion loss; microring resonator; network-on-chip; optical router; silicon photonics; system-level design; wave-guide crossing
资金
- Ministry of Science, ICT & Future Planning, Korea, under the Information Technology Research Center support program [NIPA-2014-H0301-14-1018]
An optical network-on-chip (NoC) has attracted increasing attention with the advancement of silicon photonics technology due to the explosive growth in communication traffic in system-on-chip and the diminishing returns of miniaturized metal interconnect. Compared with the traditional metallic interconnect, the optical interconnect has superior effective bandwidth, transmission latency, and power consumption. In this paper, we establish an algorithmic optical router design framework to minimize the insertion loss, which is the loss of signal power resulting from the insertion of microring resonators and waveguide crossings. By incorporating system-level considerations on the topology, routing algorithm, and traffic pattern in the optical NoC, the proposed technique provides a rapid design environment for a wide range of application-specific optical NoC architectures with minimized optical signal power loss.
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