期刊
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS
卷 23, 期 5, 页码 -出版社
WORLD SCIENTIFIC PUBL CO PTE LTD
DOI: 10.1142/S0218126614500662
关键词
Energy recovery clocking; sense-amplifier based flip-flop; sequential CMOS digital circuit
资金
- Special Man-Power Development Programme in VLSI & Related Software, Phase-II (SMDP-II)
- Ministry of Information Technology, Government of India
Energy recovery clocking is an ultimate solution to the ultra low power sequential digital circuit design. In this paper, we present a new slave latch for a sense-amplifier based flip-flop (SAFF). Energy recovery sinusoidal clock is applied to the low power SAFF. Extensive simulation based comparisons among reported and proposed SAFF are carried-out at 90 nm CMOS technology node. The proposed flip-flop operating with energy recovery single phase sinusoidal clock shows better performance. The proposed flip-flop also reduces the leakage current and glitch.
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