期刊
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS
卷 22, 期 5, 页码 -出版社
WORLD SCIENTIFIC PUBL CO PTE LTD
DOI: 10.1142/S0218126613500370
关键词
Adiabatic switching; energy estimation model; energy recovery logic; low-power CMOS circuit
资金
- SMDP-II, MCIT-Govt. of India
In this paper, an analytical model is proposed to estimate the energy consumption of n-input adiabatic logic gate. The model is based on RC linearization of the adiabatic circuit network. To validate the model expressions, simulations are carried out at 90 nm technology node using the Cadence Spectre simulator. Model validates with simulation results at a maximum error equals to 9.94%. Model expressions are also applied in comparison of energy performance of adiabatic logic and conventional CMOS logic. Proposed research work suggests the operating conditions which makes the adiabatic logic more energy efficient than conventional CMOS logic.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据