Low Surface Traps Induced Noise ZrZnO Thin-Film Transistor Using Field-Plate Metal Technology

This study proposes a high-performance top-gate ZrZnO thin-film transistor (TFT) with a novel field-plate (FP) structure. The experimental results show that the I-on/I-off ratio of the FP TFT is higher than that of a conventional structure. The leakage current and interface traps are reduced simultaneously. The measured low frequency noise spectra also demonstrated that the flicker noise generated by the surface traps can be suppressed by adopting field-plate metal structure for TFT. The field-plate ZrZnO TFT achieved a threshold voltage (V-TH) of 0.5 V and the subthreshold slope (SS) is 0.21 V/decade. In addition, the I-on/I-off ratio also reached 2.65 x 10(4) and the Hooge parameter, alpha(H), is in the range, 10(-5) to 10(-4) which is a comparatively low trap induced noise range compared to previous studies. (C) 2013 The Japan Society of Applied Physics