Data Retention Characteristics for Gate Oxide Schemes in Sub-50 nm Saddle-Fin Transistor Dynamic-Random-Access-Memory Technology

A data retention time has been investigated for various gate oxide schemes of saddle-fin (S-Fin) transistor dynamic random access memory (DRAM). The interface traps strongly affected the data retention time which was not clearly explained with a gate-induced-drain-leakage (GIDL) current as well as a junction leakage current. Despite the lower GIDL current by the thicker side-wall oxide of a dry oxidation scheme than a radical scheme, the degradation of the retention time was originated from the high interface-trap density (D-it). It is worthwhile to note that the D-it as well as the GIDL current is a still meaning parameter to analyze the data retention time. (C) 2011 The Japan Society of Applied Physics