Gate Overlap Optimization and Performance Variation for Thin-Film Transistors with Source/Drain Edge Waviness

By using ATLAS three-dimensional (3D) device simulator, we analyzed influence of gate overlap (GO) between gate and source/drain (S/D) electrodes on channel current and parasitic resistance variations of bottom-gate staggered thin-film transistors (TFTs) with wavy edge S/D electrodes that are frequently observed due to printing process variation, especially for narrow line printing. Transmission line method (TLM) analysis was performed, and showed channel current variation had a significant dependency on gate overlap. As gate overlap increases, current flow becomes less localized around peaks of the wavy edge pattern, reducing parasitic resistance. However, reduction of parasitic resistance becomes saturated when gate overlap is greater than the lateral distance over which current is collected by the contact of the wavy edge TFT. This lateral distance was found to be smaller than peak-to-peak magnitude of the wavy patterns. (C) 2010 The Japan Society of Applied Physics