A low-power four-stage amplifier for driving large capacitive loads

A four-stage amplifier with a new and efficient frequency compensation topology is presented in this paper. The new compensation scheme applies a Miller capacitor as the main negative feedback, a resistor and a capacitor in series as a load for one of the intermediate stages, and two feedforward paths. In order to design the amplifier and acquire circuit parameters, small signal analyses have been carried out to derive the signal transfer function and the pole-zero locations. The proposed amplifier was designed and implemented in a standard 90 nm CMOS process with two heavy capacitive loads of 500 pF and 1 nF. The simulation results show that when driving a 500 pF load, the amplifier has a gain-bandwidth product of 18 MHz consuming only 40.9 W. With a 1 nF capacitive load, the proposed amplifier achieves 15.1 MHz gain-bandwidth product and dissipates 55.2 W from a single 0.9 V power supply. Copyright (c) 2013 John Wiley & Sons, Ltd.