期刊
IET CONTROL THEORY AND APPLICATIONS
卷 6, 期 8, 页码 1055-1063出版社
INST ENGINEERING TECHNOLOGY-IET
DOI: 10.1049/iet-cta.2010.0443
关键词
-
资金
- National Science Fund of China for Distinguished Young Scholars [60725311]
- National Nature Science Foundation China [90820302, 61034001]
- program for Changjiang Scholars and Innovative Research Team in University [IRT1017]
To improve the on-line computational performance of model predictive control (MPC) for fast systems and/or embedded systems, this study proposes a novel scheme for the MPC controller implementation based on field programmable gate array (FPGA) and system on a programmable chip (SOPC) technology. A Nios II processor clocked at 150 MHz is embedded into the FPGA chip. A C/C++ model of the MPC algorithm which is run in the Nios II processor is created. The dual method is adopted to solve the quadratic programming (QP) problem. Based on FPGA and dSPACE (R), a rapid prototyping platform is introduced to test and verify the function and computational performance of the MPC controller. Real-time simulation results of controlling a throttle model show that a reasonable size of constrained MPC controller can be implemented on the used RCIII FPGA board.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据