期刊
IET CIRCUITS DEVICES & SYSTEMS
卷 5, 期 5, 页码 418-423出版社
INST ENGINEERING TECHNOLOGY-IET
DOI: 10.1049/iet-cds.2010.0431
关键词
-
资金
- Polish Ministry of Science and Higher Education [N N515 423034, O R00 0046 09]
An improved flipped voltage follower (FVF) and its application to a low-dropout (LDO) voltage regulator are presented. The proposed FVF improves most weaknesses of the classical one, namely its poor time response to the output current change from low to high value and poor stability for large capacitive load. The most important parameters of the modified FVF are analysed and described by analytical expressions. The parameters of the classical FVF and the improved one are compared and discussed. LDO regulator using the improved FVF is designed and implemented in AMS CMOS 0.35 mu m technology. The measurement results of a test circuit show its relatively high current efficiency of 74 and 99.93% for output current 100 mu A and 50 mA, respectively. The output voltage overshoot and undershoot are below 46 and 75 mV for output current change from 0.1 to 50 mA with the rise and fall times equal to 0.3 mu s, and load capacitance 0-100 pF.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据