期刊
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
卷 20, 期 12, 页码 2208-2219出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TVLSI.2011.2172007
关键词
Embedded and real-time systems; multi-scale; stereo image processing
资金
- EU [IST-016276-2, FP7-270436]
- Spanish Grant DINAM-VISION [DPI2007-61683]
- Spanish Grant ARC-VISION [TEC2010-15396]
- Spanish Grant ITREBA [TIC-5060]
- Spanish Grant MULTI-VISION [TIC-3873]
- Programme Alssan
- European Union [E06D101749CO]
In this work, we present a real-time implementation of a stereo algorithm on field-programmable gate array (FPGA). The approach is a phase-based model that allows computation with sub-pixel accuracy. The algorithm uses a robust multi-scale and multi-orientation method that optimizes the estimation extraction with respect to the local image structure support. With respect to the state of the art, our work increases the on-chip power of computation compared to previous approaches in order to obtain a good accuracy of results with a large disparity range. In addition, our approach is specially suited for unconstrained environments applications thanks to the robustness of the phase information, capable of dealing with severe illumination changes and with small affine deformation between the image pair. This work also includes the rectification images circuitry in order to exploit the epipolar constraints on the chip. The dedicated circuit can rectify and process images of VGA resolution at a frame rate of 57 fps. The implementation uses a fine pipelined method (also with superscalar units) and multiple user defined parameters that lead to a high working frequency and a good adaptability to different scenarios. In the paper, we present different results and we compare them with state of the art approaches.
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