Strategies to Accelerate Harmonic Minimization in Multilevel Inverters Using a Parallel Genetic Algorithm on Graphical Processing Unit

Multilevel inverters form a popular class of high-power inverters due to their high-voltage operation, high efficiency, low switching losses, and low electromagnetic interference. Meta-heuristics, such as the genetic algorithm (GA), have been used with success to compute optimal switching angles for multilevel inverters with many dc sources while minimizing several harmonics. However, these methods are computationally demanding and cannot easily be used for real-time control. In this letter, a parallel implementation of the GA on graphical processing unit (GPU) is proposed in order to accelerate the computation of the optimal switching angles for multilevel inverters with varying dc sources. Four approaches to parallelize and speed up the computation of the total harmonic distortion are presented and compared. By exploiting the massively parallel architecture of GPUs, the computation of optimal angles is accelerated by a factor of 469x compared to a sequential execution on CPU. The proposed solution optimizes multilevel inverters with 100 variable dc sources while minimizing the first 100 harmonics in 164 ms.