期刊
IEEE TRANSACTIONS ON NUCLEAR SCIENCE
卷 59, 期 4, 页码 845-850出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TNS.2012.2188040
关键词
Deep-N-Well; Si-Ge PMOS; single event upsets; SRAMs
For advanced deep sub-micron technology nodes, the use of strained-Si is fast becoming the norm. The experimental Soft Error Rate of 40 nmtechnology Deep-N-well SRAMs that incorporate strained-Si PMOS transistors are compared with the SER for 90 nm, 65 nm and 45 nm Deep-N-Well bulk CMOS SRAMs fabricated without strain. Results indicate that the total SER decreases by approximately 50% with strain. Most importantly, however, the Multiple-Cell Upset Rate decreases significantly. The factors that result in improved SER for strained SRAMs are investigated.
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