期刊
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
卷 60, 期 5, 页码 1375-1389出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TMTT.2012.2190091
关键词
CMOS, receiver; RF, wideband
资金
- Office of Naval Research (ONR)
- Defense Advanced Research Projects Agency (DARPA)
A monolithic 100-Hz-6-GHz reconfigurable vector signal analyzer (VSA) and software-defined receiver (SDR), following a two-step up-down conversion heterodyne scheme with robustness to various wideband interference scenarios and local oscillator (LO) harmonic mixing, is presented. The 130-nm CMOS chip does not require external filters or baseband processing to reduce the effect of interferences or LO harmonics. The receiver has tunable gain from -67 to 68 dB in steps of 0.5 dB, and tunable bandwidth from 0.4 to 11 MHz in steps of 0.5 MHz. The receiver sensitivity at the maximum gain is -82 dBm. A monolithic VSA/SDR enables various commercial and military wireless solutions.
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