4.6 Article Proceedings Paper

Implementation of a Four-Pole Dead-Time-Compensated Neutral-Point-Clamped Three-Phase Inverter With Low Common-Mode Voltage Output

期刊

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS
卷 45, 期 2, 页码 816-826

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TIA.2009.2013603

关键词

Electromagnetic compatibility; grounding; power systems; pulse width modulated inverters

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This paper describes the implementation of a four-pole neutral-point-clamped (NPC) three-phase inverter that produces virtually no common-mode voltage. The low common-mode voltage output is achieved by constraining the switch states of the NPC inverter to only those states that produce zero common-mode voltage in dead-time compensation, which enhances the capability of the circuit to produce low common-mode voltage by compensating common-mode voltages produced by reverse diode commutations. The low common-mode voltage performance is achieved at the expense of reduced voltage utilization and loss of dc-link voltage balance control. In order to overcome this limitation, a fourth pole and associated control are added to balance the upper and lower dc-link voltages. This paper describes the control implementations and simulation results compared to measured results used in tuning and commissioning of the system. A 450-V 78-kW system is implemented in hardware, and experimental results are provided, showing its differential mode transient and steady-state harmonic performance as well as its common-mode output voltage.

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