期刊
IEEE TRANSACTIONS ON ELECTRON DEVICES
卷 65, 期 10, 页码 4238-4244出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2018.2863730
关键词
Back-end-of-line (BEOL); fin-shaped field-effect transistor (FinFET); lattice temperature; multifin/finger nanowire FET (NWFET); self-heating; thermal resistance
资金
- Government of India, Department of Science and Technology, Government of India under TSG Grant [DST/TSG/AMT/2015/339]
- Visvesvaraya PhD Scheme of Ministry of Electronics & Information Technology, Government of India
In advanced technology nodes, an increase in power density, use of nonplanar architectures, and novel materials can aggravate local self-heating due to active power dissipation. In this paper, 3-D device simulations are performed to analyze thermal effects in fin-shaped field-effect transistors (FinFETs) and stacked-nanowire FETs (NWFETs). Based on empirically extracted equations, a new model for thermal resistance estimation is proposed, which for the first time takes into account the aggregate impact of a number of fins, number of gate fingers, number, and dimensions of stacked nanowires. We have extracted the proposed model against calibrated 3-D TCAD simulations over a range of device design variables of interest. Our results show that the model may be useful for estimation of thermal resistance in FinFETs and NWFETs with large layouts.
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