期刊
IEEE TRANSACTIONS ON ELECTRON DEVICES
卷 61, 期 7, 页码 2287-2293出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2014.2323085
关键词
Charge trapping; device modeling; high-kappa dielectric; positive bias temperature instability (PBTI)
We propose a physical model for the fast component (<1 s) of the positive bias temperature instability (PBTI) process in SiOx/HfO2 gate-stacks. The model is based on the electron-phonon interaction governing the trapping/emission of injected electrons at the preexisting defects in the dielectric stack. The model successfully reproduces the experimental time dependences of the V-TH shift on both stress voltage and temperature. Simulations allow the extraction of the physical characteristics of the defects contributing to PBTI, which are found to match those assisting the leakage current in these stacks (i.e., oxygen vacancies).
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