Scalable Virtual-Ground Multilevel-Cell Floating-Gate Flash Memory

An adequate gate coupling ratio (GCR) and compensation for floating-gate to floating-gate (FG-to-FG) coupling interference must be maintained to enable further scaling of virtual-ground multilevel-cell (MLC) FG flash memory. A high GCR of 0.6 is obtained using a novel bowl-shaped FG structure cell technology without sacrificing cell size. Increasing the GCR is important for reducing FG-to-FG coupling interference and achieving low-voltage operation. A novel array segmented virtual-ground architecture with bit-line isolation between neighboring segments and two-step programming with the channel hot electron injection threshold voltage compensation technique are proposed to reduce the number of neighboring cells that are programmed after programming a given cell, as well as the amount of threshold voltage (Vth) shift of the neighboring cells. Adoption of this programming approach realizes a reduction in the Vth shift caused by the FG-to-FG coupling interference < 25% in the bit-line direction, compared with conventional programming approaches, and the Vth shift is almost completely eliminated in the word-line direction without sacrificing program throughput. The proposed virtual-ground MLC FG cell, which is as small as 3F(2)/bit (F is the minimum feature size) is successfully implemented into a test chip with good reliability.