期刊
IEEE TRANSACTIONS ON ELECTRON DEVICES
卷 59, 期 4, 页码 1172-1182出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2012.2184545
关键词
Device modeling; dielectric breakdown; fluctuations; metal oxide; resistive switching memory (RRAM); switching parameter variation
资金
- Stanford Non-Volatile Memory Technology Research Initiative
- National Science Foundation (NSF) [ECCS 0950305]
- Nanoelectronics Research Initiative (NRI) of the Semiconductor Research Corporation through the NSF/NRI
- MSD
- C2S2 Focus Center
- Focus Center Research Program (a Semiconductor Research Corporation subsidiary)
The variation of switching parameters is one of the major challenges to both the scaling and volume production of metal-oxide-based resistive random-access memories (RRAMs). In this two-part paper, the source of such parameter variation is analyzed by a physics-based simulator, which is equipped with the capability to simulate a large number (similar to 1000) of cyclic SET-RESET operations. By comparing the simulation results with experimental data, it is found that the random current fluctuation experimentally observed in the RESET processes is caused by the competition between trap generation and recombination, whereas the variation of the high resistance states and the tail bits are directly correlated to the randomness of the trap dynamics. A combined strategy with a bilayer dielectric material and a write-verification technique is proposed to minimize the resistance variation. We describe the simulation methodology and discuss the dc results in Part I. The corroboration of the model and the device optimization strategy will be discussed in Part II.
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