Investigation of parasitic effects and design optimization in silicon nanowire MOSFETs for RF applications

The design of silicon nanowire MOSFETs (SNWTs) for RF applications is discussed in this paper based on 3-D simulation, including the impacts of the parasitic capacitances and resistance. The results indicate that large parasitic capacitances are a dominant factor for nanowire structure, which can significantly degrade the ac characteristics of SNWTs. Resistance of the ultranarrow source/drain extension (SDE) regions, which is the main contributor to the total series resistance of SNWTs, is another important factor influencing the device performance. The requirement of contact resistance of source/drain regions in SNWTs is relatively relaxed compared to the SDE regions. Considering the tradeoff between parasitic capacitances and resistance, optimization of the doping profile in SDE regions of SNWTs with 10-nm gate length is further investigated for RF applications.